module top (
    input       clk,
    input       rst_n,
    input [2:0] key_in,
    input [1:0] sw,
    //---------<rx>------------------------------------------------- 
    input       rx,
    //---------<tx>------------------------------------------------- 
    output      tx,
    //---------<sel>------------------------------------------------- 
    output[5:0] sel,
    output[7:0] dig,
    //---------<spi>------------------------------------------------- 
    output      sclk        ,
    output      mosi        ,
    output      cs_n        ,
    input       miso        
);

wire    [2:0]   key_down;
wire    [23:0]  out_data;
wire            data_vld;
wire    [7:0]   rx_data;
wire            rx_done;

fsm_key inst_fsm_key(
    .clk		(clk	 ),
    .rst_n	    (rst_n	 ),
    .key_in	    (key_in	 ),
    .key_down   (key_down)
);

spi_top inst_spi_top(
    .clk         (clk     ),
    .rst_n       (rst_n   ),
    .key_down    (key_down),
    .out_data    (out_data),
    .data_vld    (data_vld),
    .rx_data     (rx_data ),
    .rx_vld      (rx_done ),
    .sclk        (sclk    ),
    .mosi        (mosi    ),
    .cs_n        (cs_n    ),
    .miso        (miso    )
);

tx_top  inst_tx_top(
    .clk         (clk        ),
    .rst_n       (rst_n      ),
    .sw          (sw         ),
    .key_down    (key_down),
    .out_data    (out_data   ),
    .data_vld    (data_vld   ),
    .tx          (tx         )
);

sel_driver  inst_sel_dricer(
    .clk      (clk      ),
    .rst_n    (rst_n    ),
    .dis_data (out_data ),
    .sel      (sel      ),
    .dig      (dig      )
);

uart_rx inst_uart_rx(
    .clk     (clk    ),
    .rst_n   (rst_n  ),
    .rx      (rx     ),
    .sw      (sw     ),
    .rx_data (rx_data),
    .rx_done (rx_done)
);
endmodule